The present invention relates generally to semiconductor fabrication and more specifically to methods of forming dual damascene trenches.
A dual hard mask approach has been one of the most common scheme for forming dual damascene trenches in low-k dielectric layer etching processes.
One such dual hard mask practice utilizes dual hard masks with oxynitride as the top layer and silicon-carbide as the bottom layer. After the partial trench hard mask open step, the via is partially etched and stops at a buffer layer within the low-k dielectric layer. However, this scheme is not suitable for porous low-k layer dual damascene etching without using such a stop layer.
U.S. Pat. No. 5,821,169 to Nguyen et al. describes a dual damascene etch process by etching the dual damascene shape in to a hardmask and then etching the dual damascene opening into the inter-metal dielectric (IMD) layer without using an etch stop.
U.S. Pat. No. 6,043,164 to Nguyen et al. describes a dual damascene etch process by etching the dual damascene shape into a photoresist (PR) layer and then etching the dual damascene opening into the IMD layer without using an etch stop.
U.S. Pat. No. 6,054,384 to Wang et al. describes a method of etching a plurality of contiguous opening within an integrated circuit with high etch selectivity.
U.S. Pat. No. 5,632,908 to Shahid describes a method of forming an optical fiber support member.
U.S. Pat. No. 6,042,996 to Lin et al. describes a method of fabricating a dual damascene structure including forming a photoresist layer on a dielectric layer.
U.S. Pat. No. 5,753,417 to Ulrich describes a method for forming multi-level profiles from a photoresist mask.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming a dual damascene opening within a dielectric layer.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having an exposed conductive structure formed therein is provided. An etch stop layer is formed over the structure and the exposed conductive structure. A dielectric layer is formed over the etch stop layer. A hard mask layer is formed over the dielectric layer. The hard mask layer is patterned to form a partially opened hard mask layer. The partially opened hard mask layer having a trench area and a via area. The partially opened hard mask layer within the via area is patterned to form a partial via opened hard mask layer. Simultaneously, the partial via opened hard mask layer within both the trench area and the via area are etched and removed, and the dielectric layer within the via area is partial etched to form a partially opened dielectric layer to: expose a portion of dielectric layer within the trench area; and form a partial via within the partially opened dielectric layer. The partially opened dielectric layer is etched: within the trench area to form a trench; and within the via area to form a final via exposing a portion of etch stop layer. The trench and the final via forming the dual damascene opening.